In FinFET technologies at 14 nm node and beyond, the structure of the fin is critical for device performance. Narrow fin width, e.g., 5 nm to 10 nm, is the key requirement/feature that can affect the control of short channel effects and enhance transistor performance. However, narrow fins also result in a very small silicon channel volume and, therefore, an insufficient channel or halo implant dose. Consequently, FinFET devices have low threshold voltage (Vt) sensitivity to implants. Even though the implant technique is a simple and easy way to tune the Vt of a FinFET device, it is difficult to use effectively due to the FinFET device's low sensitivity.
In addition, current density at the top of a conventional trapezoidal shaped or almost triangular shaped fin is increased as gate voltage (Vg) increases. Therefore, the top of the fin can increase the ON-current (Ion) and, therefore, directly affect fin performance. A taller fin increases performance inefficiently because it does not touch the high current area, i.e., the fin top. In contrast, the bottom of a fin contributes more at low Vg, which is an OFF-state. Consequently, good control of the bottom of a fin will modulate Vt in a more efficient manner.
A known approach for implementing a multi-Vt scheme, e.g., super low threshold voltage (SLVT), low threshold voltage (LVT), regular threshold voltage (RVT), and high threshold voltage (HVT), includes using multiple work-function (WF) metals. However, the multi-metal WF scheme is challenging due to a complicated fabrication process, e.g., patterning, WF metal fill, work-function drifting, etc.
A need therefore exists for methodology enabling simple and controllable multi-Vt schemes and Vt tuning of FinFET devices and the resulting devices.